The present invention relates to a sync signal detection apparatus, and more particularly, to a sync signal detection apparatus wherein a circuit formed of the combination of plural MOS transistors is installed and consequently a discharge time of a capacitor is minimized, so that the volume of an integrated circuit element is reduced and a stable operation is performed, irrespective of the frequency bandwidth of an input signal and the duty thereof.
The sync signal detection apparatus is widely used in a switching mode power supply (SMPS) control integrated circuit, a servo integrated circuit and so on, As illustrated in FIG. 1, the conventional sync signal detection apparatus includes an external signal input terminal 11 for receiving an external sync signal, a power input terminal 12, a signal output terminal 13, a first inverter INV1 for inverting the sync signal, an NMOS transistor M11 for making the input of first inverter INV1 a low state when no signal is received in external signal input terminal 11, a PMOS transistor M21 whose operation is performed depending on the output of first inverter INV1, a capacitor C for charging and discharging the power provided by PMOS transistor M21, an RC time constant setting resistance R for setting an RC time constant, a second inverter INV2 for inverting the signal provided by capacitor C, first through third NAND gates NAND1, NAND2 and NAND3 for selectively outputting a signal, and a clock generator 14 for forming an internal signal.
Referring to FIG. 1, the conventional sync signal detection apparatus of the above structure is explained in more detail.
When no input is received in external signal input terminal 11, an input of first inverter INV1 is made a low state by NMOS transistor M11. As a result, if a high signal is applied to the gate of PMOS transistor M21 connected to the output of first inverter INV1. PMOS transistor M21 turns off. Accordingly, the input to second inverter INV2 goes low.
As a result, the output of second inverter INV2 is made high by input power VDD so as to be applied to one terminal of second NAND gate NAND2 and the output of the internal clock generator 14 connected to the other terminal of second NAND gate NAND2 passes through second NAND gate NAND2.
On the other hand, while a low signal is applied to one terminal of first NAND gate NAND1 connected to external signal input terminal 11, a low signal is applied to the other terminal of first NAND gate NAND1 by the output of PMOS transistor M21, so that a high signal is applied to one terminal of third NAND gate NAND3 connected to the output of first NAND gate NAND1. Accordingly, the signal of internal clock generator 14 is input to the other terminal or third NAND gate NAND.sub.3 to be output through signal output terminal 13.
When a sync signal is received in external signal input terminal 11, the received sync signal is applied in the input of first inverter INV1 according to the resistance characteristics of NMOS transistor M11. Then, when the inverted input signal is applied to the gate of PMOS transistor M21 connected to the output of first inverter INV1, PMOS transistor M21 performs turning-on and turning-off operations, so that input voltage VDD received in power input terminal 12 is provided to capacitor C. Thus, capacitor C is charged when PMOS transistor M21 performs the turn-on function, and the capacitor is discharged according to the RC time constant when the PMOS transistor M21 turns off.
Here, the output of PMOS transistor M21 having a frequency within a utilization frequency band is charged in capacitor C, to then be discharged according to the RC time constant. In this case, when the RC combination can be selected in order that the discharged output is maintained in a high state, a high signal is applied to the input of second inverter INV2 connected to the output of capacitor C and a low signal is applied to one terminal of the input of second NAND gate NAND2, so that the output of internal clock generator 14 connected to the other terminal of second NAND gate NAND2 is not output through second NAND gate NAND2, but the output of second NAND gate NAND2 is maintained in a high state.
On the other hand, the received sync signal is applied to one terminal of the input of first NAND gate NAND1 connected to external signal input terminal 11 and a high signal by the output of capacitor C is applied to the other terminal of the first NAND gate NAND1. As a result, the externally received sync signal is applied to one terminal of third NAND gate NAND3 connected to the output of first NAND gate NAND1, and a high signal is applied to the other terminal of third NAND gate NAND3 connected to the output of second NAND gate NAND2. Accordingly, the externally received sync signal is produced through output terminal 13 by means of the applied high signal. In such a manner, the external sync signal and the internally generated clock signal can be selectively produced.
According to the above description, the conventional sync signal detection apparatus has a problem in that when the operating frequency region of an input signal is expanded or the duty of the input signal is decreased, resistor R, capacitor C and PMOS transistor M21 each of which have a large capacity should be used. Therefore, the utilization frequency band is limited and the size of an integrated circuit element is increased.